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l 67203/l 67204 matra mhs rev. c (10/11/94) 1 introduction the l67203/204 implement a first-in first-out algorithm, featuring asynchronous read/write operations. the full and empty flags prevent data overflow and underflow. the expansion logic allows unlimited expansion in word size and depth with no timing penalties. twin address pointers automatically generate internal read and write addresses, and no external address information are required for the mhs fifos. address pointers are automatically incremented with the write pin and read pin. the 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. the retransmit pin resets the read pointer to zero without affecting the write pointer. this is very useful for retransmitting data when an error is detected in the system. using an array of eigh transistors (8 t) memory cell and fabricated with the state of the art 1.0 m m lithography named scmos, the l 67203/204 combine an extremely low standby supply current (typ = 1.0 m a) with a fast access time at 55 ns over the full temperature range. all versions offer battery backup data retention capability with a typical power consumption at less than 5 m w. for military/space applications that demand superior levels of performance and reliability the l 67203/204 is processed according to the methods of the latest revision of the mil std 883 (class b or s) and/or esa scc 9000. features first-in first-out dual port memory single supply 3.3 0.3 volts 2048 9 organisation (l 67203) 4096 9 organisation (l 67204) fast access time commercial, industrial automotive and military : 55, 60, 65 ns wide temperature range : 55 c to + 125 c 67203l/204l low power 67203v/204v very low power fully expandable by word width or depth asynchronous read/write operations empty, full and half flags in single device mode retransmit capability bi-directional applications battery back-up operation 2 v data retention ttl compatible high performance scmos technology 2k 9 & 4k 9 / 3.3 volts cmos parallel fifo
l 67203/l 67204 matra mhs rev. c (10/11/94) 2 interface block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 w i 8 i 3 i 2 i 1 i 0 xi ff q 0 q 1 q 2 q 3 q 8 gnd v cc i 4 i 5 i 6 i 7 fl /rt rs ef xo /hf q 7 q 6 q 5 q 4 r dil plastic 28 pin 300 mils dil ceramic 28 pin 600 mils so/dil (top view) (*) on request only 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 432 323130 1 14 15 16 18 19 20 17 i 2 i 1 i 0 xi ff q 0 q 1 nc q 2 i 6 i 7 nc fl /rt rs ef xo /hf q 7 q 6 i i w nc v i i 3 8 cc 4 5 q q gnd nc r q q 3 8 4 5 index 32 pin lcc and plcc lcc (top view)
l 67203/l 67204 matra mhs rev. c (10/11/94) 3 pin names names description i08 inputs q08 outputs w write enable r read enable rs reset ef empty flag names description ff full flag xo/hf expansion out/halffull flag xi expansion in fl/rt first load/retransmit vcc power supply gnd ground signal description data in (i0 - i8) data inputs for 9 - bit data reset (rs ) reset occurs whenever the reset (rs ) input is taken to a low state. reset returns both internal read and write pointers to the first location. a reset is required after power-up before a write operation can be enabled. both the read enable (r ) and write enable (w ) inputs must be in the high state during the period shown in figure 1 (i.e. t rss before the rising edge of rs ) and should not change until t rsr after the rising edge of rs . the half-full flag (hf ) will be reset to high after reset (rs ). figure 1. reset. notes : 1. ef , ff and hf may change status during reset, but flags will be valid at t rsc . 2. w and r = v ih around the rising edge of rs. write enable (w ) a write cycle is initiated on the falling edge of this input if the full flag (ff ) is not set. data set-up and hold times must be maintained in the rise time of the leading edge of the write enable (w ). data is stored sequentially in the ram array, regardless of any current read operation. once half the memory is filled, and during the falling edge of the next write operation, the half-full flag (hf ) will be set to low and remain in this state until the difference between the write and read pointers is less than or equal to half the total available memory in the device. the half-full flag (hf ) is then reset by the rising edge of the read operation. to prevent data overflow, the full flag (ff ) will go low, inhibiting further write operations. on completion of a valid read operation, the full flag (ff ) will go high after trff, allowing a valid write to begin. when the fifo
l 67203/l 67204 matra mhs rev. c (10/11/94) 4 stack is full, the internal write pointer is blocked from w , so that external changes to w will have no effect on the full fifo stack. read enable (r ) a read cycle is initiated on the falling edge of the read enable (r ) provided that the empty flag (ef ) is not set. the data is accessed on a first in/first out basis, not with standing any current write operations. after read enable (r ) goes high, the data outputs (q0 - q8) will return to a high impedance state until the next read operation. when all the data in the fifo stack has been read, the empty flag (ef ) will go low, allowing the afinalo read cycle, but inhibiting further read operations whilst the data outputs remain in a high impedance state. once a valid write operation has been completed, the empty flag (ef ) will go high after twef and a valid read may then be initiated. when the fifo stack is empty, the internal read pointer is blocked from r , so that external changes to r will have no effect on the empty fifo stack. first load/retransmit (fl /rt ) this is a dual-purpose input. in the depth expansion mode, this pin is connected to ground to indicate that it is the first loaded (see operating modes). in the single device mode, this pin acts as the retransmit input. the single device mode is initiated by connecting the expansion in (xi ) to ground. the l 67203/204 can be made to retransmit data when the retransmit enable control (rt ) input is pulsed low. a retransmit operation will set the internal read point to the first location and will not affect the write pointer. read enable (r ) and write enable (w ) must be in the high state during retransmit. the retransmit feature is intended for use when a number of writes equals or less than the depth of the fifo have occured since the last rs cycle. the retransmit feature is not compatible with the depth expansion mode and will affect the half-full flag (hf ), in accordance with the relative locations of the read and write pointers. expansion in (xi ) this input is a dual-purpose pin. expansion in (xi ) is connected to gnd to indicate an operation in the single device mode. expansion in (xi ) is connected to expansion out (xo ) of the previous device in the depth expansion or daisy chain modes. full flag (ff ) the full flag (ff ) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. if the read pointer is not moved after reset (rs ), the full flag (ff ) will go low after 2048/4096 writes. empty flag (ef ) the empty flag (ef ) will go low, inhibiting further read operations when the read pointer is equal to the write pointer, indicating that the device is empty. expansion out/half-full flag (xo /hf ) this is a dual-purpose output. in the single device mode, when expansion in (xi ) is connected to ground, this output acts as an indication of a half-full memory. after half the memory is filled and on the falling edge of the next write operation, the half-full flag (hf ) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to half of the total memory of the device. the half-full flag (hf ) is then reset by the rising edge of the read operation. in the depth expansion mode, expansion in (xi) is connected to expansion out (xo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last memory location. data output (q 0 - q 8 ) data output for 9-bit wide data. this data is in a high impedance condition whenever read (r) is in a high state.
l 67203/l 67204 matra mhs rev. c (10/11/94) 5 functional description operating modes single device mode a single l 67203/204 may be used when the application requirements are for 2048/4096 words or less. the l 67203/204 is in a single device configuration when the expansion in (xi ) control input is grounded (see figure 2). in this mode the half-full flag (hf ), which is an active low output, is shared with expansion out (xo ). figure 2. block diagram of single 2k 9 and 4k 9 fifo. (halffull flag) write (w )(r ) read data in 9 (i) data out 9 q full flag reset (ff ) (rs ) empty flag retransmit (ef ) (rt ) expansion in (xi ) hf l 67203/204 width expansion mode word width may be increased simply by connecting the corresponding input control signals of multiple devices. status flags (ef , ff and hf ) can be detected from any device. figure 3 demonstrates an 18-bit word width by using two l 67203/204. any word width can be attained by adding additional l 67203/204. figure 3. block diagram of 2048 / 4096 18 fifo memory used in width expansion mode. l 67203/204 xi l 67203/204 xi (w) write (ff ) full flag reset (r ) read (ef ) empty flag (rt ) retransmit hf 9 18 (rs ) 9 18 9 data in (i) 9 hf (q) data out note : 3. flag detection is accomplished by monitoring the ff , ef and the hf signals on either (any) device used in the width expansion configuration. do not connect any output control signals together.
l 67203/l 67204 matra mhs rev. c (10/11/94) 6 table 1 : reset and retransmit single device configuration/width expansion mode mode inputs internal status outputs mode rs rt xi read pointer write pointer ef ff hf reset 0 x 0 location zero location zero 0 1 1 retransmit 1 0 0 location zero unchanged x x x read/write 1 1 0 increment (4) increment (4) x x x note : 4. pointer will increment if flag is high. table 2 : reset and first load truth table depth expansion/compound expansion mode mode inputs internal status outputs mode rs fl xi read pointer write pointer ef ff reset first device 0 0 (5) location zero location zero 0 1 reset all other devices 0 1 (5) location zero location zero 0 1 read/write 1 x (5) x x x x note : 5. xi is connected to xo of previous device. see fig. 5. depth expansion (daisy chain) mode the l 67203/204 can be easily adapted for applications which require more than 2048/4096 words. figure 4 demonstrates depth expansion using three l 67203/204s. any depth can be achieved by adding additional 67203/204. the l 67203/204 operate in the depth expansion configuration if the following conditions are met : 1. the first device must be designated by connecting the first load (fl ) control input to ground. 2. all other devices must have fl in the high state. 3. the expansion out (xo ) pin of each device must be connected to the expansion in (xi ) pin of the next device. see figure 4. 4. external logic is needed to generate a composite full flag (ff ) and empty flag (ef ). this requires that all ef 's and all ffs be red (i.e. all must be set to generate the correct composite ff or ef ). see figure 4. 5. the retransmit (rt ) function and half-full flag (hf ) are not available in the depth expansion mode. compound expansion module it is quite simple to apply the two expansion techniques described above together to create large fifo arrays (see figure 5). bidirectional mode applications which require data buffering between two systems (each system being capable of read and write operations) can be created by coupling l 67203/204 as shown in figure 6. care must be taken to ensure that the appropriate flag is monitored by each system (i.e. ff is monitored on the device on which w is in use ; ef is monitored on the device on which r is in use). both depth expansion and width expansion may be used in this mode. data flow - through modes two types of flow-through modes are permitted : a read flow-through and a write flow-through mode. in the read flow-through mode (figure 17) the fifo stack allows a
l 67203/l 67204 matra mhs rev. c (10/11/94) 7 single word to be read after one word has been written to an empty fifo stack. the data is enabled on the bus at (twef + ta) ns after the leading edge of w which is known as the first write edge and remains on the bus until the r line is raised from low to high, after which the bus will go into a three-state mode after trhz ns. the ef line will show a pulse indicating temporary reset and then will be set. in the interval in which r is low, more words may be written to the fifo stack (the subsequent writes after the first write edge will reset the empty flag) ; however, the same word (written on the first write edge) presented to the output bus as the read pointer will not be incremented if r is low. on toggling r , the remaining words written to the fifo will appear on the output bus in accordance with the read cycle timings. in the write flow-through mode (figure 18), the fifo stack allows a single word of data to be written immediately after a single word of data has been read from a full fifo stack. the r line causes the ff to be reset, but the w line, being low, causes it to be set again in anticipation of a new data word. the new word is loaded into the fifo stack on the leading edge of w . the w line must be toggled when ff is not set in order to write new data into the fifo stack and to increment the write pointer. figure 4. block diagram of 1536 9 / 3072 9 fifo memory (depth expansion). w 6 9 ff 9 ff 9 ff 9 rs full xo ef fl ef fl ef fl xi empty 9 r v cc q l 67203/204 l 67203/204 l 67203/204 figure 5. compound fifo expansion. l 67203/204 depth expansion block l 67203/204 depth expansion block l 67203/204 depth expansion block r . w . rs q 0 q 8 q 0 q 8 q 9 q 17 q 9 q 17 q (n8) q n q (n8) q n i (n8) i n i (n8) i n i 9 i 17 i 0 i 8 i 9 i 17 i 0 i 8 notes : 6. for depth expansion block see section on depth expansion and figure 4. 7. for flag detection see section on width expansion and figure 3.
l 67203/l 67204 matra mhs rev. c (10/11/94) 8 figure 6. bidirectional fifo mode. l 67203 67204 l 67203 67204 system a system b w a ff a r b ef b hf b i a 08 q b 08 i b 08 q a 08 r a hf a ef a w b ff b
l 67203/l 67204 matra mhs rev. c (10/11/94) 9 electrical characteristics absolute maximum ratings supply voltage (vcc gnd) 0.3 v to 7.0 v . . . . . . . . . . . . . . . . . . input or output voltage applied : (gnd 0.3 v) to (vcc + 0.3 v) . . . . storage temperature : 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . operating range operating supply voltage operating temperature military vcc = 3.3 v 0.3 v 55 c to + 125 c industrial vcc = 3.3 v 0.3 v 40 c to + 85 c commercial vcc = 3.3 v 0.3 v 0 c to + 70 c automotive vcc = 3.3 v 0.3 v 40 c to + 125 c dc parameters l 67203/20455 l 67203/20460 l 67203/20465 parameter description version com ind auto mil com ind auto unit value i ccop (8) operating lt v 65 70 70 65 70 ma max () supply current l 65 70 70 65 70 ma max i ccsb (9) standby lt v 150 150 150 150 150 m a max () supply current l 150 150 150 150 150 m a max i ccpd (10) power down t v 10 20 20 10 20 m a max () current l 30 60 60 30 60 m a max notes : 8. icc measurements are made with outputs open. f = f max 9. r = w = rs = fl/rt = vih. 10. all input = vcc. parameter description l 67203/204 55 l 67203/204 65 unit value ili (11) input leakage current 1 1 m a max ilo (12) output leakage current 1 1 m a max vil (13) input low voltage 0.6 0.6 v max vih (13) input high voltage 2.0 2.0 v min vol (14) output low voltage 0.5 0.5 v max voh (14) output high voltage 2.2 2.2 v min c in (15) input capacitance 8 8 pf max c out (15) output capacitance 8 8 pf max notes : 11. 0.4 vin vcc. 12. r = vih, 0.4 vout vcc. 13. vih max = vcc + 0.3 v. vil min = 0.3 v or 1 v pulse width 50 ns. 14. vcc min, iol = 4 ma, ioh = 1 ma. 15. this parameter is sampled and not tested 100 % ta = 25 c f = 1 mhz.
l 67203/l 67204 matra mhs rev. c (10/11/94) 10 ac test conditions input pulse levels : gnd to 3.0 v input rise/fall times : 5 ns input timing reference levels : 1.5 v output reference levels : 1.5 v output load : see figure 7 figure 7. output load. to output pin 333 w 30 pf* 500 w 5 v * includes jig and scope capacitance or equivalent circuit symbol (16) symbol (17) parameter (18) (22) l 67203/204 55 l 67203/204 60 l 67203/204 65 unit min. max. min. max. min. max. read cycle trlrl trc read cycle time 70 75 80 ns trlqv ta access time 55 60 65 ns trhrl trr read recovery time 15 15 15 ns trlrh trpw read pulse width (19) 55 60 65 ns trlqx trlz read low to data low z (20) 10 10 ns twhqx twlz write low to data low z (20, 21) 15 15 ns trhqx tdv data valid from read high 5 5 5 ns trhqz trhz read high to data high z (20) 30 30 ns write cycle twlwl twc write cycle time 70 75 80 ns twlwh twpw write pulse width (19) 55 60 65 ns twhwl twr write recovery time 15 15 15 ns tdvwh tds data set-up time 30 30 30 ns twhdx tdh data hold time 0 5 10 ns reset cycle trslwl trsc reset cycle time 70 75 80 ns trslrsh trs reset pulse width (19) 55 60 65 ns twhrsh trss reset set-up time 55 60 65 ns trshwl trsr reset recovery time 15 15 15 ns retransmit cycle trtlwl trtc retransmit cycle time 70 75 80 ns trtlrth trt retransmit pulse width (19) 55 60 65 ns twhrth trts retransmit set-up time (20) 55 60 65 ns trthwl trtr retransmit recovery time 15 15 15 ns flags trslefl tefl reset to ef low 65 75 75 ns trslffh thfh, tffh reset to hf/ff high 65 75 75 ns trlefl tref read low to ef low 50 55 60 ns trhffh trff read high to ff high 50 55 60 ns tefhrh trpe read width after ef high 55 60 65 ns twhefh twef write high to ef high 50 55 60 ns twlffl twff write low to ff low 50 55 60 ns twlhfl twhf write low to hf low 65 75 75 ns trhhfh trhf read high to hf high 65 75 75 ns
l 67203/l 67204 matra mhs rev. c (10/11/94) 11 unit l 67203/204 65 l 67203/204 60 l 67203/204 55 parameter (18) (22) symbol (17) symbol (16) unit max. min. max. min. max. min. parameter (18) (22) symbol (17) symbol (16) tffhwh twpf write width after ff high 55 60 65 ns expansion twlxol txol read/write to xo low 55 60 65 ns twhxoh txoh read/write to xo high 55 60 65 ns txilxih txi xi pulse width 55 60 65 ns txihxil txir xi recovery time 10 10 ns txilrl txis xi set-up time 15 15 15 ns notes : 16. std symbol. 17. alt symbol. 18. timings referenced as in ac test conditions. 19. pulse widths less than minimum value are not allowed. 20. values guaranteed by design, not currently tested. 21. only applies to read data flow-through mode. 22. all parameters tested only. figure 8. asynchronous write and read operation.
l 67203/l 67204 matra mhs rev. c (10/11/94) 12 figure 9. full flag from last write to first read.
l 67203/l 67204 matra mhs rev. c (10/11/94) 13 figure 10. empty flag from last read to first write. figure 11. retransmit. notes : 23. ef , ff and hf may change status during retransmit, but flags will be valid at t rtc . figure 12. empty flag timing.
l 67203/l 67204 matra mhs rev. c (10/11/94) 14 figure 13. full flag timing. figure 14. half-full flag timing. figure 15. expansion out.
l 67203/l 67204 matra mhs rev. c (10/11/94) 15 figure 16. expansion in. figure 17. read data flow through mode.
l 67203/l 67204 matra mhs rev. c (10/11/94) 16 figure 18. write data flow through mode. ordering information c = commercial 0 to +70 c i = industrial 40 to +85 c a = automotive 40 to +125 c m = military 55 to +125 c s = space 55 to +125 c * on request only m = 5 v version l = 3.3 v version
1i = 28 pin dil ceramic 600 mils 3p = 28 pin dil plastic 300 mils 4j = 32 pin lcc rectangular s1 = 32 pin plcc *ui = 28 pin soj plastic 300 mils *ti = 28 pin sol plastic 300 mils 67203 = 2048 9 fifo 67204 = 4096 9 fifo l = low power v = very low power el = low power and rad tolerant ev = very low power and rad tolerant 55 ns 60 ns 65 ns blank = mhs standards /883 = mil-std 883 class b or s cb = compliant cecc 90000 level b shxxx = special customer request fhxxx = flight models (space) mhxxx = mechanical parts (space) lhxxx = life test parts (space)
the information contained herein is subject to change without notice. no responsibility is assumed by matra mhs sa for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

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